Details
| Autor: | Seyyedmohsen Seyyedrezaei |
| Titel: | Ultra-Low-Power Multiband Transmitter for Sub-GHz Short-Range Applications |
| Typ: | Dissertation |
| Fachgebiet: | Elektrotechnik |
| Auflage: | 1 |
| Sprache: | Englisch |
| Erscheinungsdatum: | 02.03.2026 |
| Lieferstatus: | lieferbar |
| Umfang: | 192 Seiten |
| Bindung: | Soft |
| Preis: | 69,00 EUR |
| ISBN: | 9783959470865 |
| Umschlag: | (vorn) |
| Inhaltsverzeichnis: | (pdf) |
Abstrakt in Englisch
The demand for low-power wireless communication systems has increased significantly in recent years, driven by applications such as the Internet of Things (IoT), wearable medical devices (WMDs), and wireless sensor networks (WSNs). These systems, particularly transmitters, often rely on batteries or energy-harvesting elements, making power consumption a critical design constraint. While batteries have limited lifetimes and require maintenance, energy-harvesting techniques offer a sustainable alternative, enabling self-sustaining operation for ultra-low-power (ULP) sensor nodes. Consequently, minimizing power consumption is paramount to extending operational longevity and enhancing energy efficiency in these systems. This research focuses on the analysis and design of an ultra-low-power transmitter in 130 nm CMOS technology, specifically targeting shortrange sub-GHz applications, including the MedRadio band at 400 MHz and ISM bands at 433 MHz and 915 MHz. By leveraging innovative circuit design techniques and system-level optimizations, this work achieves significant advancements in power efficiency and system integration. The thesis is structured into two key segments: low-power circuit block design, whose results are utilized in the second segment focused on low-power transmitter design. The first segment explores low-power circuit design methodologies, emphasizing leakage reduction and energy-efficient architecture optimization. A multi-stacked transistor topology is employed to mitigate subthreshold leakage, enabling the realization of a sub-nanowatt clock generation circuit—an essential always-on block in the transmitter. Additionally, a fast start-up crystal oscillator is introduced, achieving a start-up time of 7.6 µs through the integration of dynamic negative resistance boosting and initial motional current enhancement. These techniques effectively reduce both start-up latency and power consumption. Beyond circuit implementation, this work contributes to the theoretical foundations of ULP design by developing multiple mathematical models that characterize key circuit parameters and guide systematic power optimization. A subthreshold leakage current model is formulated for stacked structures, providing insights into its effectiveness in leakage suppression. Furthermore, mathematical models for start-up time and KVCO in ring oscillators are derived. Based on these analyses, custom-designed low-power voltage-controlled ring oscillators (VCOs) are proposed, achieving power efficiencies of 0.18 nW/kHz and 1.53 nW/kHz for three-stage and nine-stage topologies, respectively. In the second segment the integration of the fast start-up crystal oscillator enables duty-cycling of the entire transmitter chain, marking a significant step toward reducing average power consumption. By combining aggressive duty-cycling strategies with the proposed low-power circuit blocks, this work successfully demonstrates a sub-µW transmitter solution suitable for energy-constrained sub-GHz sensor node applications. The transmitter achieves a power consumption of only 435 nW at a data rate of 76.5 kb/s with a 0.9% duty-cycling rate, while it exhibits a data rate of 85 Mb/s in the continuous mode. Furthermore, its architecture is reconfigurable due to its tunable carrier frequencies, support for two modulation schemes, and the flexibility to operate with either integrated or external clock and reference signals, allowing adaptability to various application requirements.