Details

Abstrakt in Englisch

The advent of 5G technologies and Internet-of-Things (IoT) applications is pushing the annual information and communication growth rate upwards of 8%. Such a startling surge in the amount of information is putting power and performance limitations on each aspect of communication infrastructure. In the framework of hardware design, for both cellular as well as short-haul serial links, transceiver circuits are being developed to achieve highest possible energy efficiency. Transceiver circuits primarily consist of analog RF front end blocks and data converters, which convert the digital information into an analog waveform and vice versa. Conventionally, the data converter on the transmit-side of the link translates the digital data into the amplitude of an analog waveform. And the receive-side data converter simply decodes this amplitude information back into digital data. In scaled CMOS technologies, however, such amplitude-domain data converters suffer dynamic range degradation since they are forced to operate at lower supply voltages for device breakdown considerations, thereby deteriorating the noise figure of the entire link. To address this scaling-caused noise figure degradation issue, encoding the digital information in a time variable, instead of an amplitude variable, on the transmit-side, and subsequently, performing quantization in time domain on the receive-side is one promising option. This work presents several time-domain energy-efficient transmit- and receive-side data converters in 45-nm SOI CMOS node. A unique high oversampling input-delayed delay-line based receive-side data converter is first presented. This highly scalable multi-standard adaptable data converter architecture digitizes transitions/threshold crossings and inter-transition distances inside any time-domain binary input symbol sequence. The circuit works by sampling delayed replicas of a threshold-crossing binary input symbol sequence inside a differential delay-line. The resulting sampled digital word carries information of the threshold-crossings and the distances between them. The delay-line data converter has been designed and demonstrated to oversample any time-domain analog waveform data with the best reported power efficiency of 1.62 pJ/bit. To minimize the jitter, the design of the delay-element, used inside the delay-line of the data converter, as a Bessel filter is detailed and mathematical models for random and deterministic jitter inside the delay-line are developed. In addition, several active and passive bandwidth extension schemes are analyzed and their simulations are presented. Independent design and characterization of a digitally-tunable delay-element with the best reported time-resolution of 1.25 ps is also provided. For the purpose of delay-stabilization of the delay-line, the design and measurements of a wide-locking-range, 0.7-5 GHz, replica delay-line based delay-locked-loop (DLL) is also reported. One design version of this unique delay-line based data converter has also been demonstrated to function as a time-to-digital converter (TDC) with highest reported double hit resolution of 250 ps. Another version was designed and characterized as a 1:4 demultiplexer (Demux). Its comparison with other inductor-less 1:4 Demux designs shows the best achieved energy efficiency of 2.6 pJ/bit. In short, the presented delay-line based architecture has not only been demonstrated to work as a time-domain receive-side oversampling data converter but has also been proved to possess several other signal processing functionality. Next, controlled capacitor charge/discharge based unique pulsewidth modulator (PWM) and de-modulator (PWDM) are presented. This PWM modulator works by controlling the discharge rate of a capacitor. The designed PWM modulator consists primarily of a 2-bit current-steering digital-to-analog converter (DAC) and a voltage-to-time converter (VTC). The VTC operates in two phases. First phase requires the capacitor to be charged to the supply rail, while the second phase discharges the capacitor using the control voltage generated by the DAC. The rate of the capacitor discharge defines the width of the output PWM pulse. The proposed PWM modulator is demonstrated to achieve data rates upto 10 Gb/s and a record energy efficiency of 0.9 pJ/bit. The complementary PWDM consists of a time-to-voltage converter (TVC) and a 2-bit analog-to-digital converter (ADC). TVC operates in the charge phase and the discharge phase. During the charge phase an input pulsewidth-modulated (PWM) signal charges a capacitor to a certain value. The larger the width of the PWM signal, the higher the voltage developed across the charged capacitor. This capacitor voltage, which is unique to each pulsewidth, is then digitized inside a 2-bit ADC. During the discharge phase, the capacitor is allowed to completely discharge to ground. The PWDM is demonstrated to achieve the best reported energy efficiency of 0.93 pJ/bit. Finally, the tree-architecture based 4:1 multiplexer (Mux) and 1:4 Demux are designed and characterized. For the design of the latch, which is used primarily inside the key building blocks of the Mux and Demux, a power-speed optimized current-scaling methodology is provided. The results of an electromagnetic (EM) 3D field solver, which was used to simulate the high-frequency performance of the most critical data and clock paths inside the Mux and the Demux, are presented. In addition, a novel delay-line based highly scalable all-CMOS 16:1 Mux is presented and its simulations are provided. The design and analysis of this 25 Gb/s architecture shows that this delay-line Mux achieves an energy efficiency of only 160 fJ/bit, a near 10× improvement over the recently reported Muxes. The time-domain converter circuits discussed in this thesis including the input-sampled delay-line data converter and its variants, PWM/PWDM and Mux/Demux circuit blocks present several novel circuit techniques and have been demonstrated to improve the state-of-the-art.